College
Bellini College of Artificial Intelligence, Cybersecurity and Computing
Mentor Information
Dr. Dayane Reis
Description
Due to the rise of outsourced chip manufacturing, methods to protect chip designs and Intellectual Property (IP) are necessary to prevent theft and piracy by malicious actors within these intermediate firms. One such method is Logic Locking (LL), which adds circuitry that “locks” the design with a key so that the circuit only gives the correct output when provided with the correct key. The development of various attacks have allowed older LL methods, which rely on changing the placement policy of XOR/XNOR or MUX key-gates, to be broken. A newer LL solution to address this problem is TLGLock, which simplifies clusters of traditional gates into a Threshold Logic Gate (TLG) circuit and inserts keys and corresponding weights to these gates to lock them. The purpose of our research was to develop a way to attack TLGLock and recover keys used to lock circuits containing threshold key-gates. We based our work on the OMLA framework, which is an oracle-less (i.e. a functioning version of the locked circuit is not needed) attack that uses a Graph Neural Network (GNN) to learn from subgraphs associated with key-bit values. Our proposed solution identifies the unique subgraphs created with TLGLock, thus allowing the attacker to determine the functionality of the locked circuit and obtain the original design. In the future, we seek to implement and test this attack to determine its actual effectiveness in breaking TLGLock.
OAAT: OMLA-Like Approach Against TLGLock
Due to the rise of outsourced chip manufacturing, methods to protect chip designs and Intellectual Property (IP) are necessary to prevent theft and piracy by malicious actors within these intermediate firms. One such method is Logic Locking (LL), which adds circuitry that “locks” the design with a key so that the circuit only gives the correct output when provided with the correct key. The development of various attacks have allowed older LL methods, which rely on changing the placement policy of XOR/XNOR or MUX key-gates, to be broken. A newer LL solution to address this problem is TLGLock, which simplifies clusters of traditional gates into a Threshold Logic Gate (TLG) circuit and inserts keys and corresponding weights to these gates to lock them. The purpose of our research was to develop a way to attack TLGLock and recover keys used to lock circuits containing threshold key-gates. We based our work on the OMLA framework, which is an oracle-less (i.e. a functioning version of the locked circuit is not needed) attack that uses a Graph Neural Network (GNN) to learn from subgraphs associated with key-bit values. Our proposed solution identifies the unique subgraphs created with TLGLock, thus allowing the attacker to determine the functionality of the locked circuit and obtain the original design. In the future, we seek to implement and test this attack to determine its actual effectiveness in breaking TLGLock.
