College
Bellini College of Artificial Intelligence, Cybersecurity and Computing
Mentor Information
Mehran Kermani
Description
As systems grow complex, side-channel attacks pose severe threats by exploiting physical leakage, including power consumption, timing variations, and electromagnetic emissions, to infer sensitive data. To counter this, threshold implementations mask sensitive data by splitting it into randomized shares and performing intermediate computations so that no individual share reveals meaningful information. We aim to achieve a side-channel resistant architecture that eliminates statistical leakage across millions of evaluation traces. To minimize hardware overhead on the FPGA, we can time-multiplex a single protected S-box core across the cipher’s partial rounds. By decomposing the non-linear x^5 operation into cascading steps, we also aim to significantly reduce both resource consumption and fresh randomness requirements. While a standard x^5 S-box requires six shares to satisfy non-completeness, Poseidon’s HADES design uses partial rounds to restrict this complex math to one state element. This structure minimizes physical size and random bits while preserving efficiency for zero-knowledge proofs. With cryptographic systems increasingly deployed on FPGAs, protecting Poseidon against physical attacks is vital. This project secures its non-linear S-box using shared modular multiplication that maintains correctness and non-completeness. Ultimately, Poseidon’s HADES structure successfully controls thresholding overhead, offering a highly practical strategy for improving physical hardware security.
Side-Channel Protection Through Threshold Implementation: A Case Study of Poseidon
As systems grow complex, side-channel attacks pose severe threats by exploiting physical leakage, including power consumption, timing variations, and electromagnetic emissions, to infer sensitive data. To counter this, threshold implementations mask sensitive data by splitting it into randomized shares and performing intermediate computations so that no individual share reveals meaningful information. We aim to achieve a side-channel resistant architecture that eliminates statistical leakage across millions of evaluation traces. To minimize hardware overhead on the FPGA, we can time-multiplex a single protected S-box core across the cipher’s partial rounds. By decomposing the non-linear x^5 operation into cascading steps, we also aim to significantly reduce both resource consumption and fresh randomness requirements. While a standard x^5 S-box requires six shares to satisfy non-completeness, Poseidon’s HADES design uses partial rounds to restrict this complex math to one state element. This structure minimizes physical size and random bits while preserving efficiency for zero-knowledge proofs. With cryptographic systems increasingly deployed on FPGAs, protecting Poseidon against physical attacks is vital. This project secures its non-linear S-box using shared modular multiplication that maintains correctness and non-completeness. Ultimately, Poseidon’s HADES structure successfully controls thresholding overhead, offering a highly practical strategy for improving physical hardware security.
