Document Type
Patent
Publication Date
8-29-2017
Patent Number
9748837
CPC
H02M 3/07 (20130101)
Abstract
Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating is used to adaptively turn individual interleaved switched-capacitor stages of a voltage converter on and off based on workload information to improve voltage conversion efficiency. Further, as a countermeasure against machine learning based differential power analysis attacks, for example, control signals provided to a number of the interleaved switched-capacitor stages are delayed to reduce the risk of low power trace entropy (PTE). A higher PTE value is maintained regardless of the phase difference between an attacker's sampling rate and the operating frequency, providing an additional layer of security.
Application Number
14/811,033
Recommended Citation
Kose, Selcuk; Uzun, Orhun A.; and Yu, Weize, "Time delayed converter reshuffling" (2017). USF Patents. 931.
https://digitalcommons.usf.edu/usf_patents/931
Assignees
University of South Florida
Filing Date
2015-07-28