Method and apparatus for creating circuit redundancy in programmable logic devices

Authors

Praveen K. Samudrala
Srinivas Katkoori
Jeremy Ramos

Document Type

Patent

Publication Date

November 2005

Patent Number

6963217

Abstract

A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified.

Application Number

10/708,268

Recommended Citation

Samudrala, Praveen K.; Katkoori, Srinivas; and Ramos, Jeremy, "Method and apparatus for creating circuit redundancy in programmable logic devices" (2005). USF Patents. 720.
https://digitalcommons.usf.edu/usf_patents/720

Assignees

University of South Florida Honeywell Space Systems, Inc.

Filing Date

02/20/2004

Primary/U.S. Class

326/11