Document Type
Patent
Publication Date
September 2010
Patent Number
7804320
Abstract
The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.
Application Number
12/484,708
Recommended Citation
Ranganathan, Nagarajan and Bhattacharya, Koustav, "Methodology and apparatus for reduction of soft errors in logic circuits" (2010). USF Patents. 523.
https://digitalcommons.usf.edu/usf_patents/523
Assignees
University of South Florida
Filing Date
06/15/2009
Primary/U.S. Class
326/15
