Graduation Year

2020

Document Type

Thesis

Degree

M.S.Cp.

Degree Name

MS in Computer Engineering (M.S.C.P.)

Degree Granting Department

Computer Science and Engineering

Major Professor

Srinivas Katkoori, Ph.D.

Committee Member

Hao Zheng, Ph.D.

Committee Member

Mehran Mozaffari Kermani, Ph.D.

Keywords

Binary Image, Edge Computing, Image Processing

Abstract

For today’s Internet-of-Things (IoT) edge devices, there is an acute need for fast and power-efficient hardware for an image processing task. Traditional hardware solutions with sequential and/or pipelined architectures incur high latency and power. This motivates us to propose a novel in-memory computing architecture for rapid image processing. We propose a bit-sliced in-memory computing architecture for CMOS VLSI implementation for fast Sobel edge detection. To the best of our knowledge, this is the first work to propose in-memory computing based VLSI architecture foredge detection. The novelty of the proposed work is that one image can be processed in constant time irrespective of the image size. Binary images are used as input to the design. The Sobel operator equations are simplified by operator strength reduction, bit manipulation, and common term sharing across equations. The captured image is loaded into the design and all block-level operations are executed in parallel close to where the data resides. The architecture is highly modular and can be scaled for any image size. The block processing element (PE) is implemented at the layout-level with the Synopsys tool suite. For processing one block frame (3 x 3 pixel block)in 90 nm CMOS technology node, the number of logic gates is 17 with a worst-case delay of 3.52 fs and a total bounding box layout area of 158 nm2. The estimated average power dissipation is0.72μW at 0.7 V supply voltage.

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