Graduation Year
2005
Document Type
Thesis
Degree
M.S.E.E.
Degree Granting Department
Electrical Engineering
Major Professor
Arthur David Snider, Ph.D.
Committee Member
Lawrence P. Dunleavy, Ph.D.
Committee Member
Thomas M. Weller, Ph.D.
Keywords
Transcapacitance, Modeling, Nonlinear, Small signal, Large-signal, Inconsistency, Discrepancy
Abstract
The primary goal of this research is to put into code a unique approach to addressing problems apparent with nonlinear FET models which were exposed by Calvo in her work in 1994. Since that time, the simulation software for which her model was appropriate underwent a significant update, necessitating the rewriting of her model code for a few applicable FET models in a Verilog-A, making it more compatible with the new versions of software and simulators.
The problems addressed are the inconsistencies between the small-signal model and the corresponding large-signal models due to a factor called transcapacitance. It has been noted by several researchers that the presence of a nonlinear capacitor in a circuit model mathematically implies the existence of a parallel transcapacitor, if the value of its capacitance is a function of two bias voltages, the local and a remote voltage. As a consequence, simulating small signal excursions using the linear model, if the latter does not include the transcapacitance, which is inevitably present. The Calvo model attempted to improve the performance of these models by modifying terms in the charge source equations which minimize these transcapacities. Thanks to the present effort, Calvo's theory is now incorporated in the Angelov Model and can also be implemented in some other popular existing models such as Curtic, Statz and Parker Skellern models.
Scholar Commons Citation
Nicodemus, Joshua, "An Implementation of the USF/ Calvo Model in Verilog-A to Enforce Charge Conservation in Applicable FET Models" (2005). USF Tampa Graduate Theses and Dissertations.
https://digitalcommons.usf.edu/etd/795
