Graduation Year

2019

Document Type

Thesis

Degree

M.S.Cp.

Degree Name

MS in Computer Engineering (M.S.C.P.)

Degree Granting Department

Computer Science and Engineering

Major Professor

Srinivas Katkoori, Ph.D.

Committee Member

Robert Karam, Ph.D.

Committee Member

Hao Zheng, Ph.D.

Keywords

Challenge Response Pairs, Inter Chip Variation, Intra Chip Variation, Process Variations, Race Condition, Weak PUF, Strong PUF

Abstract

Physically Unclonable Functions (PUFs) are now widely being used to uniquely identify Integrated Circuits (ICs). In this work, we propose a novel Set-Reset (SR) Flip-flop based PUF design. For a NAND gate based SR flip-flop, the input condition S (Set) = 1 and R (Reset) = 1 must be avoided as it is an inconsistent condition. When S=R=1 is applied followed by S=R=0, then the outputs Q and Q' undergo race condition and depending on the delays of the NAND gates in the feedback path, the output Q can settle at either 0 or 1. Because of process variations in an IC, the NAND delays are statistical in nature. Thus, for a given SR FF based $n$-bit register implemented in an IC, when we apply S=R=1 to all flip-flops followed by S=R=0, then we obtain an $n$ bit string that can be interpreted as a signature of the chip. Due to process variations, the signature is highly likely to be unique for an IC. We validated the proposed idea by SPICE-level simulations for 90nm, 45nm, and 32nm designs for both intra- and inter-chip variations to establish the robustness of the proposed PUF. Experimental results for 16-, 32-, 64-, and 128-bit registers based on Monte-Carlo simulations demonstrate that the proposed PUF is robust. The main advantage of the proposed PUF is that there is very little area overhead as we can reuse existing registers in the design.

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