Graduation Year

2016

Document Type

Thesis

Degree

M.S.C.S.

Degree Name

MS in Computer Science (M.S.C.S.)

Degree Granting Department

Computer Science and Engineering

Major Professor

Swaroop Ghosh, Ph.D.

Co-Major Professor

Srinivas Katkoori, Ph.D.

Committee Member

Hao Zheng, Ph.D.

Keywords

Write, Bank, Sub-bank, Simulation

Abstract

Preferred especially for a Last Level Cache (LLC) due to its high retention and tolerance capabilities, Spin-Transfer Torque Random Access Memory (STTRAM) is an emerging and a promising Non-Volatile Memory (NVM) technology. To switch the magnetization of a Magnetic Tunnel Junction (MTJ), the amount of current needed is very high (~100μA per bit). For a full cache line (512-bit) write, this extremely high current results in a voltage droop in the conventional cache architecture. Due to this droop, the write operation fails especially when the farthest bank of the cache is accessed. In this thesis, we perform an analysis of the voltage droop across the STTRAM Last Level cache and then propose a new cache micro-architecture to mitigate the droop problem and make the write operations successful.

Instead of continuously writing the entire cache line (512-bit) in a single bank, the proposed architecture writes 64-bits in multiple physically separated locations across the cache. The voltage droop issue for crossbar memories such as Resistive RAM (ReRAM) has been pointed out but however, similar issue for STTRAM has never been investigated. In this study, we perform voltage droop analysis on the conventional STTRAM LLC while performing write/read operation with a simulation circuit model. Our investigation reveals that this problem exists for the write operation in a STTRAM LLC when we try to access the farthest bank in the cache. We propose a droop-mitigation Architecture which reduces the droop significantly. The effectiveness of this proposed architecture on the cache parameters such as latency and energy are compared with the conventional architecture for against various benchmarks. From the simulation results obtained (both circuit and micro-architectural), compared to the conventional architecture, the proposed architecture incurs 1.95% IPC and 5.21% energy for a 8MB last level cache.

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