Low-Power and Robust Level-Shifter with Contention Mitigation for Memory and Standalone Applications
Graduation Year
2015
Document Type
Thesis
Degree
M.S.Cp
Degree Name
MS in Computer Engineering (M.S.C.P.)
Department
Computer Engineering
Degree Granting Department
Computer Science and Engineering
Major Professor
Swaroop Ghosh, Ph.D.
Committee Member
Srinivas Katkoori, Ph.D.
Committee Member
Hao Zheng, Ph.D.
Committee Member
Jaydeep Kulkarni, Ph.D.
Keywords
eDRAM, Leakage, Wordline
Abstract
The scaling down of transistor sizes has imposed significant challenges in today's technology. Memories such as eDRAM, are experiencing poor retention time because of challenges such as reference voltage variation, high transistor leakage, and low cell capacitance. It can be seen that we must consider not only the first order effects, but also the second order effects to ensure we keep up with current technology trends such as Moore's law. In this thesis we explore various circuit level techniques on level shifters in order to achieve better retention time. With our research, we have addressed important design challenges and propose techniques that can be utilized in current and emerging technologies.
Level shifters (LS) are crucial components in low-power design where the die is segregated in multiple voltage domains. LS are used at the voltage domain interfaces to mitigate sneak path current. A less-known but very important application of LS is in high voltage drivers for designs where voltage boosting is needed for performance and functionality. We first study LS in eDRAM where LS is employed in the wordline path. Our investigation reveals that leakage power of LS can pose a serious threat by lowering the wordline voltage and subsequently affecting the speed and retention time of the eDRAM. It can also be noted that the delay of the LS under worse case process corners can cause significant functional discrepancies. We propose low-power pulsed-LS with supply gating to circumvent these issues. Our analysis indicate that pulsed-LS design can improve the worst case speed from 2.7%-43%. We extended this concept to design generic self-collapsible LSs that can be used for other applications such as voltage interfaces. The self-collapsed design in both applications improved the worst case speed from 6%-24% and 89% in some cases.
Scholar Commons Citation
Ramclam, Kenneth M., "Low-Power and Robust Level-Shifter with Contention Mitigation for Memory and Standalone Applications" (2015). USF Tampa Graduate Theses and Dissertations.
https://digitalcommons.usf.edu/etd/5555
