Graduation Year
2013
Document Type
Thesis
Degree
M.S.Cp.
Degree Granting Department
Engineering Computer Science
Major Professor
Srinivas Katkoori
Keywords
Circuit Watermarking, Finite State Machine Watermarking, Intellectual Property Protection, Sequential Circuits, Simulated Annealing
Abstract
We present a method of mitigating theft of sequential circuit Intellectual Property hardware designs through means of watermarking. Hardware watermarking can be performed by selectively embedding a watermark in the state encoding of the Finite State Machine. This form of watermarking can be achieved by matching a directed graph representation of the watermark with a sub-graph in state transition graph representation of the FSM. We experiment with three approaches: a brute force method that provides a proof of concept, a greedy algorithm that provides excellent runtime with a drawback of sub-optimal results, and finally a simulated annealing method that provides near optimal solutions with runtimes that meet our performance goals. The simulated annealing approach when applied on a ten benchmarks chosen from IWLS 93 benchmark suite, provides watermarking results with edge overhead of less than 6% on average with runtimes not exceeding five minutes.
Scholar Commons Citation
Meana, Richard William Piper, "Approximate Sub-Graph Isomorphism For Watermarking Finite State Machine Hardware" (2013). USF Tampa Graduate Theses and Dissertations.
https://digitalcommons.usf.edu/etd/4728
