Graduation Year
2003
Document Type
Dissertation
Degree
Ph.D.
Degree Granting Department
Computer Science and Engineering
Major Professor
Srinivas Katkoori, Ph.D.
Committee Member
N. Ranganathan, Ph.D.
Committee Member
Murali Varanasi, Ph.D.
Committee Member
Wilfrido Moreno, Ph.D.
Committee Member
A. N. V. Rao, Ph.D.
Keywords
clique partitioning, power management, 0-1 knapsack formulation, multi-cycling, vhdl model, tabu search
Abstract
As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage current becomes significant. A behavioral level framework for the synthesis of data-paths with low leakage power is presented. There has been minimal work done on the behavioral synthesis of low leakage datapaths. We present a fast architectural simulator for leakage (FASL) to estimate the leakage power dissipated by a system described hierarchically in VHDL. FASL uses a leakage power model embedded into VHDL leafcells. These leafcells are characterized for leakage accurately using HSPICE. We present results which show that FASL measures leakage power significantly faster than HSPICE, with less than a 5% loss in accuracy, compared to HSPICE. We present a comprehensive framework for synthesizing low leakage power data-paths using a parameterized Multi-threshold CMOS (MTCMOS) component library. The component library has been characterized for leakage power and delay as a function of sleep transistor width. We propose four techniques for minimization of leakage power during behavioral synthesis: (1) leakage power management using MTCMOS modules; (2) an allocation and binding algorithm for low leakage based on clique partitioning; (3) selective binding to MTCMOS technology, allowing the designer to have control over the area overhead; and (4) a performance recovery technique based on multi-cycling and introduction of slack, to alleviate the loss in performance attributed to the introduction of MTCMOS modules in the data-path. Finally, we propose two iterative search based techniques, based on Tabu search, to synthesize low leakage data-paths. The first technique searches for low leakage scheduling options. The second technique simultaneously searches for a low leakage schedule and binding. It is shown that the latter technique of unified search is more robust. The quality of results generated bytabu-based technique are superior to those generated by simulated annealing (SA) search technique.
Scholar Commons Citation
Gopalakrishnan, Chandramouli, "High Level Techniques for Leakage Power Estimation andOptimization in VLSI ASICs" (2003). USF Tampa Graduate Theses and Dissertations.
https://digitalcommons.usf.edu/etd/1376
