Graduation Year

2004

Document Type

Thesis

Degree

M.S.E.E.

Degree Granting Department

Electrical Engineering

Major Professor

Sanjukta Bhanja, Ph.D.

Committee Member

Yun-Leei Chiou, Ph.D.

Committee Member

Wilfrido A. Moreno, Ph.D.

Keywords

sampling, inference, Bayesian networks, simulation

Abstract

Power optimization is a crucial issue at all levels of abstractions in VLSI Design. Power estimation has to be performed repeatedly to explore the design space throughout the design process at all levels. Dynamic Power Dissipation due to Switching Activity has been one of the major concerns in Power Estimation. While many Simulation and Statistical Simulation based methods exist to estimate Switching Activity, these methods are input pattern sensitive, hence would require a large input vector set to accurately estimate Power. Probabilistic estimation of switching activity under Zero-Delay conditions, seriously undermines the accuracy of the estimation process, since it fails to account for the spurious transitions due to difference in input signal arrival times. In this work, we propose a comprehensive probabilistic switching model that characterizes the circuit's underlying switching profile, an essential component for estimating data-dependent dynamic and static power. Probabilistic estimation of Switching under Real Delay conditions has been a traditionally difficult problem, since it involves modeling the higher order temporal, spatio-temporal and spatial dependencies in the circuit. In this work we have proposed a switching model under Real Delay conditions, using Bayesian Networks. This model accurately captures the spurious transitions, due to different signal input arrival times, by explicitly modeling the higher order temporal, spatio-temporal and spatial dependencies. The proposed model, using Bayesian Networks, also serves as a knowledge base, from which information such as cross-talk noise due to simulataneous switching at input nodes can be inferred.

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