Graduation Year
2024
Document Type
Thesis
Degree
M.S.Cp.
Degree Name
MS in Computer Engineering (M.S.C.P.)
Degree Granting Department
Computer Science and Engineering
Major Professor
Srinivas Katkoori, Ph.D.
Committee Member
Hao Zheng, Ph.D.
Committee Member
Robert Karam, Ph.D.
Keywords
DTs, Edge-AI, Internet-of-Things, H-Tree, Scalability
Abstract
As the volume and diversity of Internet-of-Things (IoT) data continues to grow, traditional cloud-based processing methods face significant challenges, including latency, bandwidth constraints, and privacy concerns. Our research focuses on employing decision trees (DTs) as an intelligent filtering mechanism on the edge. Preliminary comparisons across four datasets revealed DTs are significantly more efficient than multilayer perceptrons (MLP), saving 97-98\% in area and power, leading to the selection of DT for our proposed architecture for lightweight IoT devices. We propose a novel programmable and scalable custom application specific integrated circuit (ASIC) architecture designed for Decision Tree based ML inference. Each bit-slice incorporates two 8-bit SISO input registers connected to an 8-bit comparator for data processing, the output of the comparator drives the select line of Mux, which selects the respective true and false paths. Each bit-slice can be programmed into either a leaf node or a regular node. A leaf node stores classification labels. A regular node compares a feature value with a weight value to decide between true and false paths. Given a DT model, the decision tree can be pre-programmed to store the model weights in respective tree nodes. In the inference phase, feature values are sequentially fed into the DT nodes. After the feature values are loaded the DT tree performs an inference with the classification value generated in the root node. We have implemented and validated the architecture at the layout-level using Cadence Virtuoso in 0.5$\mu$m CMOS technology node. A 3-level DT occupies roughly 90 mm² area with 10.3 mW of power consumption at a maximum clock speed of 12.8 MHz
Scholar Commons Citation
Somesula, Raaga Sai, "Programmable and Scalable Bit-Sliced VLSI Architecture for Decision Tree Based Machine Learning Edge Inference" (2024). USF Tampa Graduate Theses and Dissertations.
https://digitalcommons.usf.edu/etd/10830
