Graduation Year

2023

Document Type

Thesis

Degree

M.S.E.E.

Degree Name

MS in Electrical Engineering (M.S.E.E.)

Degree Granting Department

Electrical Engineering

Major Professor

Stephen Edward Saddow, Ph.D.

Co-Major Professor

Alexandro Castellanos, Ph.D.

Committee Member

Andrew Hoff, Ph.D.

Keywords

Classification, Counterfeiting, Digital, Measurement, Testing

Abstract

Today's society runs on modern microelectronics. Whether it is our computers, smartphones and tablets, navigation systems, and even automobiles, the impact of inferior components on our society's functioning is a well-known and serious challenge.Inferior components, in this context, refer to non-specification compliant parts that are known to enter the global supply chain either due to manufacturing/quality control errors or intentional component counterfeiting by non-OEM (original equipment manufacturer) sources. This thesis discusses the latter, which is a well-documented and growing challenge that poses a serious risk to every sector of our society. This has been further exacerbated by the global pandemic-driven manufacturing shutdowns that idled semiconductor fabrication plants worldwide and caused a severe shortage of integrated circuits (IC) globally. This is a highly complex issue. This thesis is divided into two parts so that the reader can comprehend the challenges counterfeiting poses to our society: first an overview of the counterfeiting challenge, where the most serious risks are found, along with an overview of the types of components and systems that are affected. Second, the focus is specifically on Field Programmable Gate Arrays (FPGAs), which are complex programmable logic devices that have been especially exploited by counterfeiters due to their increasing demand and elevated selling cost. A series of counterfeit detection methods employed with FPGAs will be presented, along with a novel speed-grade testing system, which aims to address the limitations of current speed-grade detection methods and offer additional opportunities for FPGA characterization and timing analysis.

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