Graduation Year

2024

Document Type

Dissertation

Degree

Ph.D.

Degree Name

Doctor of Philosophy (Ph.D.)

Degree Granting Department

Electrical Engineering

Major Professor

Gokhan Mumcu, Ph.D.

Co-Major Professor

W. Joel D. Johnson, Ph.D.

Committee Member

Jing Wang, Ph.D.

Committee Member

Stavros Vakalis, Ph.D.

Committee Member

Attila Yavuz, Ph.D.

Keywords

Broadband, Radio Frequency, True-time Delay

Abstract

This dissertation presents a systematic technique for modeling and optimization of the hierarchical time delay unit (TDU) architectures of ultra-wideband (UWB) phased antenna arrays (PAAs). The first major contribution of this dissertation is the optimization of a linear PAA by casting the problem in the standard form of integer linear programming (ILP) optimization with an objective function that targets minimizing the total number of TDUs within the RF feed network fanout while maintaining phase error and manufacturability constraints. This optimization can significantly reduce the cost, power, and complexity of UWB PAAs in contrast to prior methods that iteratively converge on a manufacturable hierarchical architecture without considering the total number of TDUs. Three linear PAA optimization examples are presented with a requirement of less than 5° phase error. These examples clearly show that there are many TDU architectures (TDU-A) that can satisfy this phase error requirement, yet only one TDU-A is superior by exhibiting the minimum number of TDUs. If the presented optimization method is omitted, the superior TDU-A is highly likely to be missed because traditional iteration based design approach almost always places the TDUs as close as possible to the antenna elements within the RF feed network fanout. On the other hand, the superior TDU-A is shown to exhibit TDUs starting from much lower levels (i.e., farther away from the antenna elements) of the RF feed network fanout.

The second contribution of this dissertation is the investigation of practical implementations for UWB PAAs. Specifically, the method is considered for linear UWB PAAs and their feed networks which include non-idealities when practical implementations of their circuit components are pursued. These non-idealities are shown to cause additional time delay errors that must be modeled within optimization to achieve the best performance from the UWB PAA. For the considered practical implementation, these delay errors are induced by frequency dependent variations in power divider isolation and load mismatch, component VSWRs, and dispersion. By properly modeling these errors in the TDU-A optimization leads to a TDU-A that has the necessary delay range required to steer the beam towards the desired wide scan angles. For experimental verification, a 16 element linear PAA TDU-A is optimized for operating from 5-30 GHz by modeling the non-idealities of the feed network that is implemented to steer the beams towards boresight, 25°, and 50°. Simulation and measured performances demonstrate the UWB operation with stable radiation patterns. Most importantly, it is shown that the physical realizations of the UWB PAAs fed with TDU-As that are optimized by accounting the non-idealities of the feed network components can be calibrated for achieving the desired scan performance.

The third contribution of this dissertation is a calibration demonstration of a 16 element linear UWB PAA as a study case. Calibration of its optimized TDU-A implementation is shown to excite each antenna element within the quantized time delay error bound. The calibration study presented assumes an instantaneous bandwidth (IBW) of 1 GHz for the UWB PAA operating from 5 to 30 GHz. It is demonstrated that variation in side lobe level (SLL) when compared to the ideal is imperceptible below -26 dB after calibration.

The final contribution of this dissertation is the expansion of the optimization to general 2D rectangular PAAs. It is shown that more than one optimal solution exists which eliminate the ability to use ILP. Therefore, a new algorithm is developed to locate an optimal architecture and two examples are presented with an objective of less than 5° phase error. The examples clearly demonstrate that many TDU-A variants satisfy the performance requirement but very few TDU-A variants achieves performance while significantly minimizing TDU and bit count.

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