Graduation Year

2022

Document Type

Dissertation

Degree

Ph.D.

Degree Name

Doctor of Philosophy (Ph.D.)

Degree Granting Department

Computer Science and Engineering

Major Professor

Robert Karam, Ph.D.

Committee Member

Hao Zheng, Ph.D.

Committee Member

Tempestt Neal, Ph.D.

Committee Member

Andrew Hoff, Ph.D.

Committee Member

Hariharan Srikanth, Ph.D.

Keywords

In-memory Computing, Edge-AI Computing, Memristor, AI ASICs, Non-volatile Memory

Abstract

The recent surge of data-intensive applications has stretched the performance and energy limit of today’s traditional computing system. The massive amount of data generated by data-intensive applications is not processed at the same speed due to bandwidth mismatch between the faster processing unit and slower memory. Memory access and communication bandwidth can be identified as the primary bottlenecks. Consequently, these two bottlenecks make up most of the total energy consumption. In light of this, we explore energy-efficient computing for data-intensive applications. We examine different aspects of two computing systems, such as in-memory computing and AI-enabled edge computing, more popularly known as edge-AI computing. We further the energy efficiency of edge-AI computing by implementing it on ASICs. The primary goal of this research is to explore these two paradigms that would enable energy-efficient computing of data-intensive applications by mitigating the number of times memory is accessed and by lessening the bandwidth requirement.

To pave the way for in-memory computation, we look at different aspects of it concerning its implementation. The emerging non-volatile memory such as memristor is one such enabler. In this work, we propose a VHDL-based framework that enables us to quickly perform behavioral simulation and estimate the dynamic energy consumption and speed of any large memristive crossbar array. The individual memristor model is embedded with power and delay numbers obtained from a detailed memristor model. The proposed framework supports two prominent logic styles and can easily be extended for other emerging technologies.

To further the energy-efficient implementation, we propose a novel approach to address the fanout overhead problem. Instead of copying the logic value as inputs to the driven memristors, we propose that the controller reads the logic value and then applies it in parallel to the driven memristors. In addition, we examine the impact of high-energy radiation during the in-memory logic computation. We analyze the impact of radiation-induced Single Event Transients (SETs) on such architectures. The SETs generated can result in undesirable effects while executing a logic function. We also analyze SET-induced crosstalk noise due to interconnect coupling effects in the array. Detailed SPICE level simulations on crossbar array have shown that SETs resulting from single and multiple particle strikes can worsen NOR/NOT gate’s execution delay, trigger state drift in memristor(s), or flip memristor state (i.e., single event upset).

High data rate detectors play an integral part in scientific research, and their development is actively pursued at High Energy Physics (HEP) facilities around the world. Edge Machine Learning (ML) offers the ability to reduce data rates by integrating ML algorithms into Application Specific Integrated Circuits (ASICs) on the front-end electronics. This work explores a set of neural network architectures for predicting the peak amplitudes in the detector’s sensor response. We design and synthesize several MLP, CNN, and pruned MLP-based neural networks, comparing their inference accuracy, power consumption, and area targeting for minimal latency and energy consumption. The neural networks are synthesized in a commercial 65nm process. The effect of quantizing the network’s weights and biases on hardware performance and area is reported. We also conduct design space exploration to compare design alternatives in terms of accuracy, power, performance, and area.

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