Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications
Document Type
Article
Publication Date
12-2015
Keywords
application-specific integrated circuit (ASIC), reliability, smart infrastructures
Digital Object Identifier (DOI)
https://doi.org/10.1109/TVLSI.2014.2382715
Abstract
Efficient cryptographic architectures are used extensively in sensitive smart infrastructures. Among these architectures are those based on stream ciphers for protection against eavesdropping, especially when these smart and sensitive applications provide life-saving or vital mechanisms. Nevertheless, natural defects call for protection through design for fault detection and reliability. In this paper, we present implications of fault detection cryptographic architectures (Pomaranch in the hardware profile of European Network of Excellence for Cryptology) for smart infrastructures. In addition, we present low-power architectures for its nine-to-seven uneven substitution box [tower field architectures in GF(33)]. Through error simulations, we assess resiliency against false-alarms which might not be tolerated in sensitive intelligent infrastructures as one of our contributions. We further benchmark the feasibility of the proposed approaches through application-specific integrated circuit realizations. Based on the reliability objectives, the proposed architectures are a step-forward toward reaching the desired objective metrics suitable for intelligent, emerging, and sensitive applications.
Was this content written or created while at USF?
No
Citation / Publisher Attribution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 23, issue 12, p. 2804-2812
Scholar Commons Citation
Mozaffari Kermani, Mehran; Azarderakhsh, Reza; and Aghaie, Anita, "Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications" (2015). Computer Science and Engineering Faculty Publications. 25.
https://digitalcommons.usf.edu/esb_facpub/25
