Document Type
Article
Publication Date
1998
Digital Object Identifier (DOI)
https://doi.org/10.1155/1998/93106
Abstract
High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.In this paper, we present an accurate power estimation technique for register transfer level designs generated by high level synthesis systems. The technique has four main aspects: (1) Each RT level component used in high level synthesis is characterized for average switched capacitance per input vector. This data is stored in the RT level component library. (2) Using user-specified stimuli, the given behavioral description is simulated and event activities of various operators and carriers are measured. Then, the behavioral specification is submitted to the synthesis system and a number of alternative RTL designs meeting speed, space and throughput rate constraints are generated. (3) Event activity of each component in an RT level design is estimated using the event activities measured at the time of behavior level profiling and the structure of the RTL design itself. (4) The event activities so obtained are then used to modulate the average switched capacitances of the respective RT level components to obtain an estimate the total switched capacitance of each component.Detailed power estimation procedures for the three different parts of RTL designs, namely, data path, controller and interconnect are presented. Experimental results obtained from a variety of designs show that the power estimates are within 3%–10% of the actual power measured by simulating the transistor level designs extracted from mask layouts.
Rights Information
This work is licensed under a Creative Commons Attribution 3.0 License.
Was this content written or created while at USF?
Yes
Citation / Publisher Attribution
VLSI Design, v. 7, art. 093106
Scholar Commons Citation
Katkoori, Srinivas and Vemuri, Ranga, "Architectural Power Estimation Based on Behavior Level Profiling" (1998). Computer Science and Engineering Faculty Publications. 121.
https://digitalcommons.usf.edu/esb_facpub/121
