Digital Manufacturing and Performance Testing for Military Grade Application Specific Electronic Packaging (ASEP)

Document Type

Conference Proceeding

Publication Date

2016

Keywords

digital manufacturing, 3D printing, 3D printed electronics, printed circuit structures, structural electronics, personalized electronics

Digital Object Identifier (DOI)

https://doi.org/10.4071/isom-2016-WP13

Abstract

This paper will discuss the development of additive manufacturing as a process integration methodology for printed electronics and 3D printed structures. This integration enables the ability to move from printed circuit boards (PCBs) to printed circuit structures (PCS). Historically packaging has been identified as a hierarchical (or levels) approach to interconnect electronic products or systems. Level one packaging addresses the interconnection between bare die and the module while level four moves up in the packaging chain to connections between subassemblies. With the advent of digital manufacturing and emergence of more robust materials, the enabling technology provides a manufacturing tool for building electronic packages with integrated passives (some printed) and actives. This further enables the capability to adjust the form factor to the mission or product requirements - also known as personalization. This ability to become form factor agnostic has produced the ability for printing or digitally manufacturing application specific electronic packages, ASEPs. With this emerging capability it begs the question of reliability and in particular to qualification for harsh environment applications. This paper will discuss the application of current standards, Mil-Std-883 or JESD93 for example and how these might be applied to ASEPs and to also explore the development of new or hybridization of current standards.

Was this content written or created while at USF?

Yes

Citation / Publisher Attribution

International Symposium on Microelectronics, v. 2016, p. 250-266

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