College
Bellini College of Artificial Intelligence, Cybersecurity and Computing
Mentor Information
Santosh Pandey
Description
Security-sensitive workloads on shared processors can expose vulnerability-relevant behavior through branch predictors, caches, prefetchers, and shared memory resources. This project investigates whether hardware performance monitoring unit (PMU) counters can provide lightweight indicators of such behavior on the ARM-based NVIDIA DGX Spark, which uses Cortex-X925 and Cortex-A725 CPU cores. Unlike prior work that uses counters to detect active attacks, this study evaluates whether normalized PMU metrics can characterize conditions that increase vulnerability exposure without claiming exploitability.
We map Spectre-style speculation, cache side channels, memory-access-pattern leakage, and shared-resource contention to branch miss rate, cache and LLC miss rates, IPC, and stall rates. Experiments using microbenchmarks and AES T-table and GnuPG ElGamal workloads showed that stronger branch disruption, cache pressure, and contention produced stronger PMU signatures. Branch miss rate increased from 0.43% to 9.35%, LLC miss rates reached 96.8%, and GnuPG ElGamal experienced a 17.3% slowdown under pressure. These results support PMU counters as feasibility signals for deeper security analysis.
Hardware Performance Counters as Vulnerability Signals on NIVDIA DGX Spark
Security-sensitive workloads on shared processors can expose vulnerability-relevant behavior through branch predictors, caches, prefetchers, and shared memory resources. This project investigates whether hardware performance monitoring unit (PMU) counters can provide lightweight indicators of such behavior on the ARM-based NVIDIA DGX Spark, which uses Cortex-X925 and Cortex-A725 CPU cores. Unlike prior work that uses counters to detect active attacks, this study evaluates whether normalized PMU metrics can characterize conditions that increase vulnerability exposure without claiming exploitability.
We map Spectre-style speculation, cache side channels, memory-access-pattern leakage, and shared-resource contention to branch miss rate, cache and LLC miss rates, IPC, and stall rates. Experiments using microbenchmarks and AES T-table and GnuPG ElGamal workloads showed that stronger branch disruption, cache pressure, and contention produced stronger PMU signatures. Branch miss rate increased from 0.43% to 9.35%, LLC miss rates reached 96.8%, and GnuPG ElGamal experienced a 17.3% slowdown under pressure. These results support PMU counters as feasibility signals for deeper security analysis.
