Graduation Year


Document Type




Degree Name

MS in Electrical Engineering (M.S.E.E.)

Degree Granting Department

Electrical Engineering

Major Professor

Srinivas Katkoori, Ph.D.

Co-Major Professor

Wilfrido Moreno, Ph.D.

Committee Member

Nasir Ghani, Ph.D.


Weak PUF, Strong PUF, Slices, LUTs, Bitstream


Physical Unclonable Functions (PUF) are used for authentication and key generation to obtain a unique signature and are widely used in hardware security applications. In this work, we propose Set-Reset Flip-flop (SRFF) based PUF for FPGAs. We exploit the race around condition of the SRFF to obtain a one-bit signature output which is a function of feedback path delays. In deep sub-micron technology node, delay variations on an FPGA device are significant due to manufacturing process variations. Thus, an SRFF output value is a function of its location on the FPGA device. We implement registers of various bit widths and extract signature in different locations on a device. We demonstrate that the signatures are spatially unique for sufficiently large register bit widths. We have experimented with fifteen (15) Spartan-6 FPGA devices (45 nm technology node) to study the uniqueness, uniformity, randomness, and robustness of the PUF as the Spartan-6 FPGA devices are very well known for the low power applications and good performance. We explored the Xilinx 14.7 ISE tool and used some of its in-built core tools like Chip-scope to synthesize higher bitstreams.