Graduation Year


Document Type




Degree Name

Doctor of Philosophy (Ph.D.)


Electrical Engineering

Degree Granting Department

Electrical Engineering

Major Professor

Sanjukta Bhanja, Ph.D.

Co-Major Professor

Syed M. Alam, Ph.D.

Committee Member

Gokhan Mumcu, Ph.D.

Committee Member

Selcuk Kose, Ph.D.

Committee Member

Sudeep Sarkar, Ph.D.


Authentication, Coupling, Logic-in-Memory, MTJ, PUF, STT Clocking


Computer memories now play a key role in our everyday life given the increase in the number of connected smart devices and wearables. Recently post-CMOS memory technologies are gaining significant research attention along with the regular ones. Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) is one such post-CMOS memory technology with a rapidly growing commercial interest and potential across diverse application platforms. Research has shown the ability of STT-MRAM to replace different levels of memory hierarchy as well. In brief, STT-MRAM possesses all the favorable properties of a universal memory technology. In this dissertation we have explored the roles of this emerging memory technology beyond traditional storage. The purpose is to enhance the overall performance of the application platform that STT-MRAM is a part of. The roles that we explored are computation and security. We have discussed how the intrinsic properties of STT-MRAM can be used for computation and authentication. The two properties that we are interested in are the dipolar coupling between the magnetic memory cells and the variations in the geometries of the memory cell. Our contributions here are a 22nm CMOS integrated STT-MRAM based logic-in-memory architecture and a geometric variation based STT-MRAM signature generation. In addition we have explored the device physics and the dynamics of STT-MRAM cells to propose a STT based clocking mechanism that is friendlier with the logic-in-memory setup. By investigating the logic layouts and propagation style in the architecture, we have also proposed different techniques that can improve the logic density and performance of the architecture.