Graduation Year


Document Type




Degree Granting Department

Computer Science

Major Professor

N.Ranganathan, Ph.D.

Committee Member

Murali Varanasi, Ph.D.

Committee Member

Dewey Rundus, Ph.D.


optimization, estimation


The increasing need for low-power computing devices has led to the efforts to optimize power in all the components of a system. It is possible to achieve significant power optimization at the software level through instruction reordering during the compilation phase. In this thesis, we have designed and implemented a novel instruction scheduling technique, called FD-ISLP, aimed at reducing the software power consumption. In the proposed approach for instruction scheduling, we modify the force-directed scheduling technique used in high-level synthesis of VLSI circuits to derive a latency-constrained algorithm that reorders the instructions in a basic block of assembly code in application software to reduce power consumption due to its execution. The scheduling algorithm takes the data dependency graph (DDG) for a given basic block and a power dissipation table (PDT), which is generated by characterizing the instruction set architecture. We model power, commonly referred to as software power in literature, as a force to be minimized by relating the inter-instruction power cost as the spring constant,k,and the change in instruction probability as the displacement,x, in the force equation f = k * x. The salient feature of our algorithm is that it accounts for the global effect of any tentative scheduling decision, which avoids a solution being trapped in a local minima. The power estimates are obtained through using a tool set, called Simple-Power. Experimental results indicate that our technique accounts for an average of 12.68 % savings in power consumption over the original source code for the selected benchmark programs.