Graduation Year

2023

Document Type

Dissertation

Degree

Ph.D.

Degree Name

Doctor of Philosophy (Ph.D.)

Degree Granting Department

Computer Science and Engineering

Major Professor

Hao Zheng, Ph.D.

Committee Member

Srinivas Katkoori, Ph.D.

Committee Member

Mehran Mozaffari Kermani, Ph.D.

Committee Member

Wilfrido Moreno, Ph.D.

Committee Member

Arman Sargolzaei, Ph.D.

Committee Member

Kaiqi Xiong, Ph.D.

Keywords

DSE, Message flows, Model-inference, SoC, Validation

Abstract

The rapid growth of complex system-on-chip (SoC) designs has presented unprecedented opportunities and challenges in electronic design automation (EDA). This dissertation explores two facets of electronic design automation: message flow specification mining using data mining and natural language processing (NLP) and high-level synthesis (HLS) acceleration using different machine learning (ML) methods. It also discusses an ML model co-optimization method for energy-efficient hardware implementation.

Effective SoC design validation relies heavily on message flow specifications. This dissertation presents an efficient technique for synthesizing finite state automaton (FSA) models from SoC execution traces. The synthesized models can provide valuable insights into the on-chip communication protocols of complex designs.

NLP models present a unique opportunity for SoC execution trace analysis. A novel method using state-of-the-art large language models (LLMs) to explore true causality relations among the interblock communication messages is discussed in this dissertation. This method addresses certain challenges that cannot be overcome by the model synthesis method.

HLS translates high-level software descriptions of hardware designs into efficient hardware implementations. To expedite this process, this dissertation investigates the application of deep neural networks (DNNs) for HLS acceleration. Leveraging expert classifiers optimizes design choices, resulting in superior field programmable gate array (FPGA) implementation, thus reducing design time and enhancing overall design efficiency.

Energy efficient or green ML model design methodologies are vital for resource-constrained environments such as Internet of Things (IoT) devices and edge computing platforms. This dissertation contributes to developing methods for green ML hardware implementation design by integrating different model optimization and operation transformation techniques. These methodologies focus on reducing the size of the model and energy consumption while preserving the accuracy of inference.

This dissertation explores several challenges in EDA and proposes ML techniques to address them. It demonstrates that combining data mining with model synthesis enhances our understanding of system executions, trace analysis through LLMs can uncover true causality relations among the system-level messages, HLS can be accelerated using DNNs, and energy-efficient ML model or green AI can be designed utilizing optimal word length and operation transformation. This dissertation shows that machine learning helps address several critical challenges in SoC design validation and HLS.

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