Graduation Year


Document Type




Degree Granting Department

Computer Engineering

Major Professor

Srinivas Katkoori, Ph.D.

Committee Member

Nagarajan Ranganathan, Ph.D.

Committee Member

Hao Zheng, Ph.D.


Field Programmable Gate Array, Reconfigurable Logic, Evolutionary Algorithms, Verilog, Xilinx Virtex-II Pro


The field of FPGA design is ever-growing due to costs being lower than that of ASICs, as well as the time and cost of development. Creating programs to run on them is equally important as developing the devices themselves. Utilizing the increase in performance over software, as well as the ease of reprogramming the device, has led to complex concepts and algorithms that would otherwise be very time-consuming when implemented on software. One such focus has been towards a search and optimization algorithm called the genetic algorithm. The proposed approach is to take an existing application of the genetic algorithm on an FPGA, developed by Fernando et al. [1], and create several instances of it to make a parallel genetic algorithm engine. The genetic algorithm cores are interfaced with a controller module that will control the flow of data between them to implement the parallel execution. Both coarse-grained and fine-grained parallelism are tested and results collected to find the best performance when compared to the single core design. Initial experimental results show some improvement over the number of generations required to reach the optimal fitness level, as well as more significant improvement for the number of generations needed for the average fitness to reach the optimal level.