Graduation Year


Document Type




Degree Granting Department

Electrical Engineering

Major Professor

Don Morel, Ph.D.

Committee Member

Christos Ferekides, Ph.D.

Committee Member

Elias K. Stefanakos, Ph.D.

Committee Member

Luis H. Garcia-Rubio, Ph.D.

Committee Member

Joseph Stanko, Ph.D.


photovoltaics, cgs, cis, cigs, indium


The goal of this research project was to contribute to the understanding of CuGaSe2/CdS photovoltaic devices, and to improve the performance of these devices.

The initial part of the research dealt with the optimization of a Sequential Deposition process for CuIn(Ga)Se2 absorber formation. As an extension of this, a recipe (Type I Process) for CuGaSe2 absorber layer fabrication was developed, and the deposition parameters were optimized. Electrical characterization of the thin films and completed devices was carried out using techniques such as Two-Probe and Three-Probe Current-Voltage, Capacitance-Frequency, Capacitance-Voltage, and Spectral Response measurements. Structural/chemical characterization was done using XRD and EDS analysis.

Current densities of up to 15.2 mA/cm2, and Fill Factors of up to 58% were obtained using the Type I CuGaSe2 Process. VOC's, however, were limited to less than 700 mV. Several process variations, such as changes in the rate/order/temperature of depositions and changes in the thickness of layers, resulted in little improvement. With the aim of breaking through this VOC performance ceiling, a new absorber recipe (Type II Process) was developed. VOC's of up to 735 mV without annealing, and those of up to 775 mV after annealing, were observed. Fill Factors were comparable to those obtained with Type I Process, whereas the Current Densities were found to be reduced (typically, 10-12 mA/cm2, with the best value of 12.6 mA/cm2). This performance of Type II devices was correlated to a better intermixing of the elements during the absorber formation.

To gain an understanding of the performance limitations, two simulation techniques, viz. SCAPS and AMPS, were used to model our devices. Several processing experiments and SCAPS modeling indicate that a defective interface between CuGaSe2 and CdS, and perhaps a defective absorber layer, are the cause of the VOC limitation. AMPS simulation studies, on the other hand, suggest that the back contact is limiting the performance. Attempts to change the physical back contact, by changes in the absorber processing, were unsuccessful.

Processing experiments and simulations also suggest that the CuGaSe2/CdS solar cell involves a true heterojunction between these two layers.