Graduation Year
2004
Document Type
Thesis
Degree
M.S.E.E.
Degree Granting Department
Electrical Engineering
Major Professor
Srinivas Katkoori, Ph.D.
Co-Major Professor
Moreno Wilfrido, Ph.D.
Committee Member
Sanjukta Bhanja, Ph.D.
Keywords
Time domain, C/A code, Sliding correlator, Acquistion, Tracking
Abstract
Global Positioning System is a technology which is gaining acceptance. Originally developed for military purposes, it is being used in civilian applications such as navigation, emergency services, etc. A system-on-chip application merges different functions and applications on a single substrate. This project models a GPS receiver for a system on chip application. The GPS receiver, developed as a core, is intended to be a part of a navigation tour guide being developed. The scope of this work is the GPS C/A code on the L1 carrier. The digital signal processing back-end in a GPS receiver is modelled in this work. VHDL modeling of various communiation sub-blocks, detection and demodulation schemes is done. A coherent demodulation of the GPS signals is implemented. GPS receiver calculates the position based on the data collected from four satellites. Given four satellites, acquisition of the data from the signals is performed and data demodulated from the same. Synthetic data is generated for validation purposes. Code acuqisition and tracking of the GPS C/A signal is implemented. Cadence NC-Launch VHDL simulator is used to validated the behavioral VHDL model.
Scholar Commons Citation
Daita, Viswanath, "Behavioral VHDL Implementation of Coherent Digital GPS Signal Receiver" (2004). USF Tampa Graduate Theses and Dissertations.
https://digitalcommons.usf.edu/etd/1005
