Generalized Parallel CRC Computation on FPGA

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Conference Proceeding

Publication Date



altera FPGA, computer arithmetic, error control coding

Digital Object Identifier (DOI)



The cyclic redundancy check (CRC) is a popular error detection code (EDC) used in many digital transmission and storage protocols. Most existing digit-serial hardware CRC computation architectures are based on one of the two well-known bit-serial CRC linear feedback shift register (LFSR) architectures. In this paper, we present and investigate a generalized CRC formulation that incorporates negative degree terms. Through software simulations, we identify useful formulations that result in reduced time and/or area complexity CRC circuits compared to the existing non-retimed approaches. Implementation results on an Altera field-programmable gate array (FPGA) device are reported. We conclude that the proposed approach is most effective when the digit size is greater than the generator polynomial degree.

Altera FPGA, Computer arithmetic, error control coding

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Citation / Publisher Attribution

2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE), p. 107-113