Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform
Document Type
Conference Proceeding
Publication Date
10-2011
Keywords
FPGA platform, Fault detection scheme, Grøstl, SHA-3, reliable hardware implementation
Digital Object Identifier (DOI)
https://doi.org/10.1109/DFT.2011.60
Abstract
The third round of competition for the SHA-3 candidates is ongoing to select the winning function in 2012. Although much attention has been devoted to the performance and security of these candidates, the approaches for increasing their reliability have not been presented to date. In this paper, for the first time, we propose a high-performance scheme for fault detection of the SHA-3 round-three candidate Grostl which is inspired by the Advanced Encryption Standard (AES). We propose a low-overhead fault detection scheme by presenting closed formulations for the predicted signatures of different transformations of this SHA-3 third-round finalist. These signatures are derived to achieve low overhead and include one or multi-bit parities and byte/word-wide predicted signatures. The proposed reliable hardware architectures for Grostl are implemented on Xilinx Virtex-6 FPGA family to benchmark their hardware and timing characteristics. The results of our evaluations show high error coverage and acceptable overhead for the proposed scheme.
Was this content written or created while at USF?
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Citation / Publisher Attribution
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), p. 325-331
Scholar Commons Citation
Mozaffari Kermani, Mehran and Reyhani-Masoleh, Arash, "Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform" (2011). Computer Science and Engineering Faculty Publications. 63.
https://digitalcommons.usf.edu/esb_facpub/63
