Error Detection Reliable Architectures of Camellia Block Cipher Applicable to Different Variants of Its Substitution Boxes

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Conference Proceeding

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reliability, Application-specific integrated circuit (ASIC), block cipher, Camellia, fault detection

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Different security properties are provided by cryptographic architectures to protect sensitive usage models such as implantable and wearable medical devices and nano-sensor nodes. Nevertheless, the way such algorithms are implemented could undermine the needed security and reliability aims. Unless the reliability of architectures is guaranteed, natural or malicious faults can undermine such objectives. Noting this, in this paper, we present error detection approaches for the Camellia block cipher taking into account its linear and non-linear sub-blocks. We also tailor the presented error detection architectures towards the desirability of using different variants of the S-boxes based on the security and reliability objectives. The merit of the proposed approaches is that (a) they can be tailored and applied to look-up table-based and composite field-based S-boxes, (b) their reliability vs. overhead can be fine-tuned based on the usage models, and (c) they result in high error coverage and acceptable overheads for performance and implementation metrics. We present the results of error simulations and application-specific integrated circuit (ASIC) implementations to benchmark the efficiency of the presented schemes.

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Citation / Publisher Attribution

Hardware-Oriented Security and Trust (AsianHOST), IEEE Asian, 19-20 December 2016, 6 p.