FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over GF(2m) and Their Applications in Trinomial Multipliers
systolic structure, All one polynomial (AOP), finite field multiplication, irreducible trinomials, low register complexity, Montgomery algorithm
Digital Object Identifier (DOI)
Systolic all-one-polynomial (AOP) multipliers usually suffer from the problem of high register complexity, especially in field-programmable gate array (FPGA) platforms where the register resources are not that abundant. In this paper, we have shown that the AOP-based systolic multipliers can easily achieve low register-complexity implementations and the proposed architectures can be employed as computation cores to derive efficient implementations of systolic Montgomery multipliers based on trinomials. First, we propose a novel data broadcasting scheme in which the register complexity involved within existing AOP-based systolic multipliers is significantly reduced. We have found out that the modified AOP-based structure can be packed as a standard computation core. Next, we propose a novel Montgomery multiplication algorithm that can fully employ the proposed AOP-based computation core. The proposed Montgomery algorithm employs a novel precomputed-modular operation, and the systolic structures based on this algorithm fully inherit the advantages brought from the AOP-based core (low register complexity, low critical-path delay, and low latency) except some marginal hardware overhead brought by a precomputation unit. The proposed architectures are then implemented by Xilinx ISE 14.1 and it is shown that compared with the existing designs, the proposed designs achieve at least 61.8% and 47.6% less area-delay product and power-delay product than the best of competing designs, respectively.
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Citation / Publisher Attribution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 25, issue 2, p. 725-734
Scholar Commons Citation
Chen, Pingxiuqi; Nazeem Basha, Shaik; and Mozaffari Kermani, Mehran, "FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over GF(2m) and Their Applications in Trinomial Multipliers" (2017). Computer Science and Engineering Faculty Publications. 28.